Director, ASIC Design

Credo Technology Group Ltd.-posted about 1 month ago

$210,000 - $240,000/Yr

Full-time • Director

San Jose, CA

501-1,000 employees

Computer and Electronic Product Manufacturing

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As a Director, ASIC Design you will lead the development of advanced ASIC solutions for next-generation data communication products. In this role, you will be responsible for driving chip development from concept to production, managing high-performing teams, and ensuring successful execution of complex ASIC projects. You will provide technical leadership, collaborate across functions, and deliver high-quality silicon that meets stringent performance and reliability standards. You will work on all aspects of front-end ASIC design, including project definition, micro-architecture specification, and design and verification of complex logic blocks. Additionally, you will partner with PD, DFT, STA, and PV teams to ensure successful tape-outs and work closely with system teams for chip bring-up.

Lead chip development: Oversee design, verification, validation, and physical implementation of complex ASIC projects to ensure bug-free, high-quality silicon.
Manage design & verification teams for large, high-speed ASICs.
Project planning & execution: Develop and maintain project schedules, ensuring timely delivery.
Provide technical leadership through all phases of ASIC development: architecture, micro-architecture, RTL design, verification, timing closure, and physical design.
Collaborate with PD, DFT, STA, PV, and system teams for successful tape-outs and chip bring-up.

MS degree in Electrical Engineering or Computer Science with 15+ years of relevant experience in ASIC design.
Deep understanding of digital logic design and complex synchronous/asynchronous interfaces.
Proficiency in Verilog/SystemVerilog RTL design.
Knowledge of synthesis and static timing analysis.
Experience developing testbenches and test cases; familiarity with UVM.
Hands-on experience with chip bring-up and validation.
Proven track record of successful production tape-outs.
Familiarity with DFT methodology and physical design flow.
Hands-on experience with STA and timing closure.
Strong planning, estimation, and communication skills.
Ability to lead and mentor teams effectively.

Expertise in scripting languages (Python, Tcl, Perl, Shell).
Knowledge of EDA tools (Synopsys, Cadence, Mentor).
Experience with high-speed interfaces or SerDes.

This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

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