Digital, Mixed Signal IC Design Engineer, Principal

Marvell • Santa Clara, CA

47d

About The Position

As a Digital IC Design Principal Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Storage, Security, and Networking. You'll be part of a digital team making a big impact on this organization. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in engineering implementation spec writing from system requirements, RTL design, verification, synthesis, static timing analysis.

Requirements

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 8-15 years of related professional experience.
• Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
• Strong understanding of SoC architecture, processor cores, memory and peripheral interfaces through hands on prior experience.
• Extensive experience in Verilog/VHDL, Spyglass and Quality checks of the implemented RTL for LINT, CDC.
• Hands on experience in interpretive language such as Perl/Python.
• Proven track record of delivering production-quality designs on aggressive development schedules.

Nice To Haves

• Domain expertise in IEEE/UCIe/CXL/PCIe protocols, DDR memory controllers is a plus.

Responsibilities

• Improve the design methodology and flow.
• RTL designs for various type of SerDes IPs ranging for 448Gbps data-rates for different applications.
• Document modeling and verification results for formal review.
• Collaborate with Analog/DSP/DV/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
• Be a key contributor to bridge the gap between digital and analog design flow.
• Provide the support to the product teams, for both pre and post silicon

Benefits

• flexible time off
• 401k
• year-end shutdown
• floating holidays
• paid time off to volunteer

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Industry: Computer and Electronic Product Manufacturing
• Number of Employees: 5,001-10,000 employees