The position involves defining block-level design specifications, which include interface protocols, block diagrams, transaction flows, and pipeline architecture. The candidate will participate in chip-level architecture definition with a focus on ALS datapath design, performing power, performance, and area (PPA) trade-off analysis using Spyglass. Responsibilities also include completing RTL coding of functional blocks in alignment with full-chip integration timelines, performing RTL design and coding using Verilog/SystemVerilog, and conducting functional and performance simulation debugging. The role requires executing Lint, CDC (Clock Domain Crossing), UPF (Unified Power Format), and formal verification (FV) checks to ensure design quality and robustness. Additionally, the candidate will develop and contribute to test plans and perform coverage analysis at both block and SoC levels, implement and verify analog sensor timing behavior models using SystemVerilog, and conduct timing control design and verification for image sensor arrays and analog-related circuits using Verilog and Python. The position also involves performing schematic and behavioral logic equivalence checks using Cadence Virtuoso, full-chip integration and verification using industry-standard tools such as SimVision and Verdi, and collaborating with the back-end team to support floor planning, DFT (Design-for-Test), and timing closure. The candidate will participate in logic synthesis and assist in achieving timing and power closure across design blocks, perform FPGA prototyping, chip bring-up, and system-level validation, and debug silicon using a combination of FPGA platforms and Python-based test environments.