Digital Design Engineer - mixed-signal/DSP (Internship 2026)

Astera Labs Early Career • San Jose, CA

2d

About The Position

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are looking for a Digital Design and/or Verification Engineering Intern with a strong interest in mixed-signal and high-speed DSP to join our ASIC team developing next-generation compute and networking solutions in advanced CMOS process nodes. The ideal candidate will have a solid background in digital hardware design, along with exposure to signal processing concepts and mixed-signal interfaces. In this position, you will work on the design and/or verification of mixed-signal digital blocks, collaborating closely with analog, system, and verification engineers. You will gain hands-on experience with high-performance signal paths and techniques used in advanced SerDes.

Requirements

• Pursuing a BS or MS in EE/CS, or related field.
• Coursework or experience in Digital Design, DSP, or Mixed-Signal Systems.
• Hands-on experience with Verilog/SystemVerilog and digital design or verification flows.
• Familiarity with Python, MATLAB, or C/C++ for modeling, analysis, or automation.

Nice To Haves

• Understanding of DSP fundamentals such as filtering, equalization, or adaptive algorithms.
• Exposure to mixed-signal interfaces and real-number modeling (SystemVerilog RNM, Verilog-AMS).
• Knowledge of high-speed I/O architectures (Ethernet, PCIe, DDR, HBM).
• Familiarity with Synopsys EDA tools.

What This Job Offers

• Career Level: Intern
• Number of Employees: 251-500 employees