Digital ASIC Prototyping Engineer

Ciena • Atlanta, GA

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About The Position

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute: The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital ASIC prototyping engineer who will be involved in both the design and verification of the WaveLogic ASICs. As a member of a team of digital design engineers, verification engineers and architects, your role as a digital ASIC prototyping engineer will be to adapt strategic portions of the ASICs onto various FPGA prototyping platforms with the goal of improving or complementing their verification. As a digital ASIC prototyping engineer, you are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects You will produce an implementation specification document and have it reviewed by your peers and architects You are accountable for the creation and integration of ASIC RTL source code, algorithms and functions targeting FPGAs You are responsible for designer testing of your code as well as debugging of your code during simulation and regression verification as part of the prototype FPGA development process You will assist the verification team in determining coverage specifically targeted to the FPGA prototyping platforms You are responsible for crafting timing constraints, and applying advanced FPGA floorplanning and timing closure techniques to optimize the porting of ASIC code to the FPGA You will be involved in lab validation of the FPGA prototype as well as support to our software development team during initial product bring-up You are expected to report on status updates on a regular basis The Must Haves: Electrical or computer engineering degree at the BEng/BSc or MEng/MSc level Experience with digital design synthesis, STA, timing closure and asynchronous clock domain crossing, specifically with major FPGA vendors' tools Proficiency with System Verilog for design Ability to methodically solve complex technical problems, specifically around FPGA implementation Excellent understanding of timing/power/area analysis and trade-offs A highly motivated self-starter, able to work independently, while being a team player Excellent organization, written and oral (English) communication skills Familiarity with digital (including formal) verification methods Assets: Experience with digital silicon design backend process Experience with digital design for low power Experience with standards and protocols such as OTN, B100G, Ethernet Experience with using Jira for bug tracking and GIT for source code management and revision tracking Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++, System C The above lists are intended to describe the general nature and level of work by the selected candidate. They are not intended to be an exhaustive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience. The annual pay range for this position is $119,900 - $191,500 USD. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. Discover how Ciena's unique blend of deep humanity and relentless innovation creates an exceptional workplace culture. Explore CienaLife.

Requirements

• Electrical or computer engineering degree at the BEng/BSc or MEng/MSc level
• Experience with digital design synthesis, STA, timing closure and asynchronous clock domain crossing, specifically with major FPGA vendors' tools
• Proficiency with System Verilog for design
• Ability to methodically solve complex technical problems, specifically around FPGA implementation
• Excellent understanding of timing/power/area analysis and trade-offs
• A highly motivated self-starter, able to work independently, while being a team player
• Excellent organization, written and oral (English) communication skills
• Familiarity with digital (including formal) verification methods

Nice To Haves

• Experience with digital silicon design backend process
• Experience with digital design for low power
• Experience with standards and protocols such as OTN, B100G, Ethernet
• Experience with using Jira for bug tracking and GIT for source code management and revision tracking
• Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++, System C

Responsibilities

• adapt strategic portions of the ASICs onto various FPGA prototyping platforms with the goal of improving or complementing their verification
• read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects
• produce an implementation specification document and have it reviewed by your peers and architects
• creation and integration of ASIC RTL source code, algorithms and functions targeting FPGAs
• designer testing of your code as well as debugging of your code during simulation and regression verification as part of the prototype FPGA development process
• assist the verification team in determining coverage specifically targeted to the FPGA prototyping platforms
• crafting timing constraints, and applying advanced FPGA floorplanning and timing closure techniques to optimize the porting of ASIC code to the FPGA
• involved in lab validation of the FPGA prototype as well as support to our software development team during initial product bring-up
• report on status updates on a regular basis

Benefits

• medical, dental, and vision plans
• participation in 401(K) (USA) & DCPP (Canada) with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company-paid holidays
• paid sick leave
• vacation time

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level