DFT Engineer

Intel • Boxborough, MA

344d

About The Position

Intel is seeking DFT engineers to work on the latest server products DFT architecture and execution. The role involves developing logic design, register transfer level (RTL) coding, simulation, and providing DFT timing closure support, as well as test content generation and delivery to manufacturing for various DFx content including SCAN, MBIST, and BSCAN. The position requires collaboration in defining architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed. Additionally, the engineer will develop HVM content for rapid bring up and ramp to production on automatic test equipment (ATE).

Requirements

• The candidate must be pursuing a Bachelor's Degree in Computer Science, Computer Engineering, Electrical Engineering, Electronics Engineering.

Nice To Haves

• Related technical discipline with 6+ months of relevant industry experience.
• Knowledge of Programming languages: C++, and/or python.
• Knowledge of Computer Architecture.

Responsibilities

• Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).
• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).
• Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
• Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
• Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
• Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.
• Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

Benefits

• Competitive pay
• Stock options
• Bonuses
• Health benefits
• Retirement plans
• Vacation time

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level
• Industry: Computing Infrastructure Providers, Data Processing, Web Hosting, and Related Services
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees