The DFT Design Engineering Architect at Cadence is responsible for leading the Design for Test (DFT) team in the development and implementation of DFT strategies for SoC/ASIC designs. This role requires extensive experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST), and automatic test pattern generation (ATPG). The architect will work collaboratively with cross-functional teams to ensure high-quality DFT solutions from RTL to GDSII and silicon debug.