The DFT Design Engineering Architect at Cadence is responsible for leading the Design for Test (DFT) team in the development and implementation of DFT strategies for SoC/ASIC designs. This role requires extensive experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST), and automatic test pattern generation (ATPG). The architect will work collaboratively with cross-functional teams to ensure high-quality DFT solutions from RTL to GDSII and silicon debug.
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Job Type
Full-time
Career Level
Senior
Industry
Professional, Scientific, and Technical Services
Education Level
No Education Listed