Design Verification Lead - Security Engineering

Qualcomm-posted 3 months ago
$222,600 - $333,800/Yr
Full-time • Senior
Remote • Santa Clara, CA
5,001-10,000 employees
Computer and Electronic Product Manufacturing
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As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation-creating a smarter, more connected future for all. We are seeking a seasoned Design Verification (DV) Lead to join our Security Engineering team, where you will provide strategic oversight and technical leadership for the verification of security-critical hardware subsystems. This is a high-impact role responsible for driving DV execution, ensuring quality and completeness, and mentoring a team of engineers to deliver world-class secure hardware solutions.

  • Lead and manage DV efforts for security-focused subsystems, ensuring alignment with architectural and system-level requirements.
  • Define and own verification strategy, methodology, and execution plans across multiple functional domains.
  • Oversee development of scalable and reusable verification environments, including stimulus generation, checkers, monitors, assertions, and coverage models.
  • Guide the creation and execution of detailed test and coverage plans based on architecture and micro-architecture specifications.
  • Drive design bring-up, regression setup, and debug efforts, ensuring robust verification coverage and timely closure of issues.
  • Provide technical mentorship and leadership to DV engineers, fostering best practices and continuous improvement.
  • Collaborate cross-functionally with architects, designers, and software teams to ensure comprehensive validation of security features.
  • Report DV progress and quality metrics to stakeholders, ensuring transparency and accountability.
  • Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
  • 15+ years of experience in SOC-level or core-level verification, with a strong track record of leading DV teams and delivering high-quality silicon.
  • Deep understanding of APB/AXI/SPI protocols, handshake mechanisms, cross-clock domains, and clock gating.
  • Solid grasp of memory organization, fault-tolerant design, parity schemes, and error detection/correction mechanisms.
  • Experience with SystemVerilog/UVM, formal verification, assertions, and silicon bring-up.
  • Familiarity with ARM or RISC-V processor architectures, NoC designs, and micro-architectures.
  • Proficiency with industry-standard verification tools: simulators, coverage tools, waveform viewers, and mixed-signal verification.
  • Strong scripting skills in Python/Perl and working knowledge of UNIX/Linux environments.
  • Experience in writing test plans, portable testbenches, transactors, and assembly code.
  • Security experience (e.g., cryptographic algorithms, secure boot flows) is a plus, but not required.
  • Competitive annual discretionary bonus program
  • Opportunity for annual RSU grants
  • Comprehensive benefits package designed to support success at work, at home, and at play
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