Design Verification Intern

Cadence Design Systems • Austin, TX

282d

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. As a Design Verification Intern, you will understand design specifications and develop test/coverage plans. You will be involved in the development of constrained random verification environments and verification components, as well as writing tests, sequences, functional coverage, and assertions to meet verification goals.

Requirements

• Understanding of SV/UVM.
• Good knowledge of Verilog/VHDL/C/C++.
• Experience in any scripting language (Perl/Python/Shell).
• Good debugging skills.

Nice To Haves

• Familiarity with ARM/CPU architectures.
• Good knowledge of protocols like UART, I2C, SPI, JTAG.
• Knowledge of AMBA protocols (AXI/AHB/APB).
• Hands-on experience in writing tests/sequences/functional coverage.
• Prior experience with Cadence verification tools and flows.

Responsibilities

• Understand design specifications and develop test/coverage plans.
• Develop constrained random verification environments and verification components.
• Write tests, sequences, functional coverage, and assertions to meet verification goals.

What This Job Offers

• Job Type: Full-time
• Career Level: Intern
• Industry: Professional, Scientific, and Technical Services