Design Verification Engineering Manager

Intel Corporation • Austin, TX

1d • Hybrid

About The Position

Intel is seeking a highly qualified candidate to lead a chiplet verification team in a dynamic and forward-thinking organization focused on next-generation semiconductor product development. Our team focuses on being nimble, adaptable, lean and efficient to drive cutting-edge, customer impacting technology development. We embrace innovative and efficient methodologies that drive at-scale product execution. Advance your career with cutting-edge verification techniques including coverage-driven verification, formal methods, and performance analysis. Lead custom SystemVerilog/UVM development, master industry-standard EDA tools, architect verification strategies for complex ASICs, and mentor emerging talent while independently driving verification closure. Join our fast-paced semiconductor team where your technical leadership shapes next-generation chip development through comprehensive methodologies and innovative verification solutions. Transform challenging projects into career-defining achievements. If you are passionate about building products faster and more efficiently than anyone else on the planet, we want you on our team.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, computer science, or in other relevant STEM related degree.
• 6+ years of experience in ASIC/FPGA design verification
• Strong understanding of object-oriented programming (OOP) principles and their application in SystemVerilog UVM or other verification methodologies.
• Developing UVM and/or Formal based verification architectures and methodologies.
• Experience with industry standard protocols (AMBA AXI/AXI-S/CHI and communication protocols (e.g., PCIe, Ethernet, UART, SPI, I2C/I3C))
• Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent).
• Familiarity with coverage-driven verification, constrained-random testing and strong debugging skills.
• Experience with scripting languages.

Nice To Haves

• Graduate/post-graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree with overall 8+ yrs. of experience.
• Skilled in various validation concepts and debug techniques relevant to ASIC/FPGA domain.
• Collaborative, able to communicate well with counter parts and stakeholders. Strong written and verbal communication skills.
• Strong analytical ability and problem-solving skills.
• Experience in defining testbench architecture, constrained random verification methodologies.
• Experience in processor-based verification using C/C++ with UVM-based verification environments.
• Define and execute validation of IPs and/or SOC from spec to tape-in including setting verification strategy, creating test bench and components, defining test plan, writing tests, debugging, coverage and analysis.
• Low power experience (e.g., UPF).
• Experience in AMBA, CXS stream, DDR, PCIe and/or Ethernet, UCIe protocols.
• Experience in EDA tools and reusable testbench for subsystem and SoC that deploys 3rd party VIPs.
• Experience with formal verification techniques and tools is an asset.

Responsibilities

• Lead and manage a team of design verification engineers, cultivating a culture of collaboration, accountability, and innovation
• Define Project Specific Verification Strategy: Defines and implement scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs. Ensure meeting the required coverage levels and confirm to microarchitecture specifications.
• Lead Verification Execution: Create detailed test plans and drives technical reviews with design and architecture teams to validate these plans and proofs.
• Executes verification plan: Implement and run block/subsystem/cluster/soc simulation models to verify the design, analyze power and performance, and identify bugs.
• Investigate and Resolve Bugs: Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
• Collaborate Across Teams: Work closely with chiplet architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Enhance Future Verification Methodologies: Continuously improves existing functional verification infrastructure and methodologies.
• Absorbs learnings: From post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products.
• Lead and mentor others: inspire and guide junior engineers, fostering their growth and development. Your expertise will be instrumental in cultivating a collaborative and innovative environment where every team member thrives.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees