Apple-posted 2 months ago
TX
5,001-10,000 employees

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

  • Ensure bug-free first silicon for part of the SoC / IP.
  • Develop detailed test and coverage plans based on the micro-architecture.
  • Develop verification methodology suitable for the IP.
  • Ensure a scalable and portable verification environment.
  • Develop verification environment components such as stimulus, checkers, assertions, trackers, and coverage.
  • Execute verification plans, including design bring-up and DV environment bring-up.
  • Enable regression features and debug test failures.
  • Develop block, IP, and SoC level test-benches.
  • Track and report DV progress using metrics including bugs and coverage.
  • Utilize LLM and related technologies for efficient execution and improved quality.
  • BS degree in technical subject area.
  • Minimum 10 years relevant industry experience or equivalent.
  • Deep knowledge of OOP, SystemVerilog, and UVM.
  • Deep knowledge in developing scalable and portable test-benches.
  • Strong experience with verification methodologies and tools such as simulators, waveform viewers, and coverage collection.
  • Working experience using LLMs for efficiency and quality.
  • Experience with power-aware (UPF) or similar verification methodology.
  • Excellent knowledge of one of the scripting languages such as Python, Perl, or TCL.
  • Experience with serial protocols such as PCIe or USB.
  • Experience with parallel protocol such as DDR.
  • Knowledge of formal verification methodology.
  • Knowledge of emulation for verification technologies.
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