Design Verification Engineer

Apple • Beaverton, OR

116d

About The Position

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Requirements

• BS degree in technical subject area.
• Minimum 3 years of proven experience or equivalent.

Nice To Haves

• Strong knowledge of OOP, SystemVerilog, and UVM.
• Strong knowledge in developing scalable and portable test-benches.
• Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, gate level simulations.
• Some working experience using LLMs for efficiency and quality.
• Experience with power-aware (UPF) or similar verification methodology.
• Knowledge of one of the scripting languages such as Python, Perl, or TCL.
• Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required.
• Knowledge of formal verification methodology is a plus but not required.
• Knowledge of emulation for verification technologies is a plus but not required.

Responsibilities

• Ensure bug-free first silicon for part of the SoC / IP.
• Develop detailed test and coverage plans based on the micro-architecture.
• Develop verification methodology suitable for the IP.
• Ensure a scalable and portable verification environment.
• Develop verification environment components such as stimulus, checkers, assertions, trackers, and coverage.
• Implement verification plans, including design bring-up and DV environment bring-up.
• Enable regression for all features under your care.
• Debug test failures.
• Develop block, IP, and SoC level test-benches.
• Track and report DV progress using various metrics, including bugs and coverage.
• Utilize LLM and related technologies for efficient execution and improved quality.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees