Design Verification Engineer - Viasat Government
About The Position
At Viasat Government - Secure Network Systems (SNS) you’ll work with highly motivated engineers in an exciting and dynamic environment. You will use your engineering experience to develop the next generation of advanced communications products and systems. As a Design Verification Engineer, you will work closely with our RTL development engineers, system architects, and software engineers to verify functional correctness and robustness of the RTL powering our next generation, FPGA-based secure communications systems. You will be responsible for RTL verification at both the unit and system level, as well as creating and maintaining the verification environment and test cases. A key aspect of this job is closely collaborating across both small and large project teams to understand the functional and performance goals of the system, use cases and edge cases, and using that knowledge to develop effective test plans and test cases. Experience in RTL design and development and FPGA implementation is a plus, and the ideal candidate will have the opportunity to work on both verification and design/implementation tasks. What’s the day-to-day like for this candidate? Own the verification of custom RTL blocks, subsystems, and full FPGA-level functionality Work with RTL design engineers and system architects to define verification plans based on system specifications, design goals, and use cases Develop and maintain verification environment in SystemVerilog/UVM including constrained-random, directed, and system-level testbenches Develop and maintain stimulus generators, drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces Work closely with RTL design engineers to triage and resolve bugs, owning and driving technical issues to resolution Collect and report code and functional coverage Maintain regular simulation regressions
Requirements
- Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
- 5+ years experience in hardware verification using SystemVerilog/UVM
- Proven success verifying complex RTL designs in industry-standard flows, including creation and maintenance of verification environment, test benches, and test cases
- Proficient in SystemVerilog, UVM, and common simulation and debug tools including Siemens Questa
- Experience with Object Oriented Programming
- Experience with industry standard EDA tools (Cadence, Synopsys, and/or Mentor)
- Foundational knowledge of digital logic and timing considerations
- Strong written and verbal communication skills, ability to work with a geographically distributed team
- Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
- Desire to be a member of a team, collaborating on large system designs
- Work independently, take initiative, and take ownership of tasks and results
- US citizenship required
- Active United States Secret Security Clearance
- Ability to travel up to 10%
Nice To Haves
- MSEE or MSCE degree preferred
- Experience with Programmable Logic EDA tools, including AMD/Xilinx Vivado, Altera Quartus, and Microchip Libero
- Experience with the FPGA design process, from the requirements phase to documentation, design, implementation of source code, place & route, testing in hardware, and integration
- Familiarity with TCL, Perl, Python or another scripting language
- Experience with high-speed interfaces like SERDES, DDR2/3/4, LVDS
- Proven experience in debugging, diagnosing, and solving embedded designs issues
- Experience and familiarity with Linux-based development environments
Responsibilities
- Own the verification of custom RTL blocks, subsystems, and full FPGA-level functionality
- Work with RTL design engineers and system architects to define verification plans based on system specifications, design goals, and use cases
- Develop and maintain verification environment in SystemVerilog/UVM including constrained-random, directed, and system-level testbenches
- Develop and maintain stimulus generators, drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces
- Work closely with RTL design engineers to triage and resolve bugs, owning and driving technical issues to resolution
- Collect and report code and functional coverage
- Maintain regular simulation regressions
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
