Design Verification Engineer
Voltai•Palo Alto, CA
91d
About The Position
In this role, you will ensure silicon correctness through UVM-based environments, formal methods, and emulation. You’ll collaborate with machine learning research engineers, verification engineers, and physical design teams to develop next-generation simulation engines for edge conditions and corner cases to guarantee robustness.
Requirements
- 5+ years of experience in SystemVerilog/UVM
- Functional coverage
- Assertions
- Regression infrastructure
- Debug tools
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
Number of Employees
1-10 employees
