Design Verification Engineer

Marvell Technology • Boise, ID

160d • $90,400 - $133,760

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Marvell Custom Solutions develops cutting-edge solutions for large AI, cloud data center, and telecom customers. The SoCs encompass best-in-class performance, advanced die-to-die and packaging technology, and optimized low-power techniques. As part of the Marvell Data Center Design Verification Team, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use highly advanced technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers' specifications whether they're a major hyperscaler company or telecom organization, etc.

Requirements

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 2+ years of related professional experience.
• OR Master's degree in Computer Science, Electrical Engineering or related fields.
• Knowledge of SoC verification and test bench development using UVM, System Verilog, C/C++, and DPI.
• Understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations, data structure).
• Must have effective interpersonal and teamwork skills.
• Participate in problem solving and quality improvement activities.
• Demonstrate initiative and a bias for thoughtful action.
• Grounded, detail-oriented, always backs up ideas with facts.
• Must have the ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.

Responsibilities

• Implement simulation test bench in UVM.
• Develop and execute test-plans for verifying correctness and performance of the design.
• Own and debug failures in simulation to root-cause problems.
• Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations.

Benefits

• Flexible time off
• 401k
• Year-end shutdown
• Floating holidays
• Paid time off to volunteer

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Bachelor's degree