Design Verification Engineer Intern

Rambus • San Jose, CA

76d • $25 - $46 • Hybrid

About The Position

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Design Verification Engineer Intern to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

Requirements

• Major in EE, CS or related.
• Proficient in Verilog, systemverilog and UVM.
• Familiar with Linux environment and the industry's prevailing EDA tools.
• Have better understanding of Verification methodology and concepts.
• Have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
• Have excellent communication skills (both written and oral) and cross-team/function collaboration capability.
• Experienced in code coverage and functional coverage closure.
• Strong problem-solving skills.

Responsibilities

• Understand the architecture of the chip and functional blocks.
• Develop/maintain verification environments for chip level verification and enhance/use the automated regression infrastructures.
• Create testplan and develop test cases/sequences in UVM.
• Debug functional issues in the DUT based on the good understanding of the architectural specification.
• Closely work with Design/Architecture/Circuit team to identify and align with the Milestones and Quality metrics of the project.

What This Job Offers

• Career Level: Intern
• Industry: Computer and Electronic Product Manufacturing
• Education Level: No Education Listed
• Number of Employees: 251-500 employees