ARM-posted 3 months ago
$241,100 - $326,100/Yr
Hybrid • Austin, TX

Arm System IP enables designers to build Arm AMBA systems that are high performance, power efficient and reliable. Configurable for many different applications, System IP is the right choice for your system whether it is a high-efficiency IoT endpoint or a high-performance server SoC. The collection of silicon proven interconnects, security IP, system controllers, debug and trace and IP tooling are all designed, validated and optimized to be used with Arm Cortex processors and Arm Mali Multimedia IP. Built upon the open AMBA interface standard, Arm System IP provides design teams with the foundation for building better systems. Job Overview: The Arm CoreLink series of products include our scalable and highly configurable packetized Network-on-Chip (NoC) as well as the Coherent Mesh Network which is designed for intelligent connected systems across a wide range of applications including networking infrastructure, storage, server, HPC, automotive, and industrial solutions. Our group is a dedicated verification expert in cache coherency and memory sub-system verification to drive our future product development. This is an individual contributor role working with our verification team here in our Austin Design Center!

  • Build and maintain detailed verification plans/strategies for our next generation interconnect designs.
  • Work alongside architects and designers to debug and develop new features balancing the needs of multiple partners in our product development cycle.
  • Architect and develop sophisticated and efficient SystemVerilog/UVM based test benches.
  • Debug functional regression failures, close coverage and drive improvements.
  • Bachelors, Masters or PhD in Electrical/Computer Engineering or Computer Science
  • 8 to 15 years of experience in verification/RTL design.
  • Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI).
  • Previous experience in specification, creation, and debug of System Verilog/UVM constrained-random testbenches.
  • Demonstrated ability, experience and successful track record verifying sophisticated designs in the area of cache coherency, multi-processor designs and memory sub-systems.
  • Strong software engineering skills including understanding of object-oriented programming, data structures, and algorithms.
  • Proficiency with functional coverage verification methods.
  • Strong debug skills and ability to use modern techniques, methodologies and EDA tools.
  • Knowledge of high speed protocols such as PCI Express (PCIe), SATA, USB and Ethernet.
  • Excellent knowledge of scripting languages such as Python or Perl.
  • Experience in Formal Verification techniques is a plus.
  • Competitive salary range of $241,100-$326,100 per year.
  • Flexible hybrid working environment.
  • Commitment to diversity and equal opportunities.
  • Support for accommodations during the recruitment process.
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