Design for Test Engineering Intern - Bachelors Degree

Marvell Technology-posted 3 months ago
$28 - $55/Yr
Full-time • Intern
Boise, ID
Computer and Electronic Product Manufacturing
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Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The Custom and Compute Business Unit in Marvell is a world leader in advanced node semiconductor engineering. The team is developing high core-count AI compute platforms, 5G and 6G acceleration silicon, and custom ASIC designs for industry leading customers. Designs are large, complex, and challenge current design and manufacturing limits. Multi-die, 2.5D and 3D designs guarantee that Marvell remains at the forefront, delivering the highest and most integrated solutions that customers require.

  • Work with a high-performing DFT/DV team within a DFT organization.
  • Design verification at block and full-chip of DFT IP inserted at RTL level.
  • Develop UVM test cases when new DFT RTL is added into a design.
  • Gain experience in DFT architecture and ensure thorough testing of underlying logic in RTL form.
  • Develop scripts to abstract technical details of DFT architecture into control files.
  • Work with JTAG, 1687, and evolving chiplet to chiplet test busses.
  • Automate the creation of functional test patterns deployed on ATE using 1687 ICL/PDL.
  • Debug high speed IOs including DDR and SERDES.
  • Collaborate with designers and IP developers to understand test requirements.
  • Use Siemens EDA tools to insert scan and memory BIST, and verify these inserted test elements.
  • Working towards a Bachelor's degree in Computer Science, Electrical Engineering or related fields.
  • VLSI/SCAN/ATPG and UVM/Verification coursework preferred.
  • Desire to work with scan/ATPG, memory BIST, using Siemens tools.
  • Desire to work with System Verilog, UVM, Verification Test Plans, Coverage Driven Verification, Code Coverage, verification environments, test case simulation and debug.
  • Medical, dental and vision coverage.
  • Perks and discount programs.
  • Wellness & mental health support including coaching and therapy.
  • Paid holidays.
  • Paid volunteer days.
  • Paid sick time.
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