Design Engineering Architect

Cadence Design Systems • San Jose, CA

2d

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design Engineering Architect – Roles & Responsibilities Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations Drive architecture decisions aligned with JEDEC standards, protocols, and compliance requirements Good understanding of PHY/IO circuit architecture including TX/RX, clocking, termination, power delivery, and signal integrity trade‑offs Act as a customer‑facing technical architect during pre‑sales, evaluations, and post‑delivery support, clearly articulating architecture choices and trade‑offs Collaborate closely with Sales, Marketing, and Program teams to support customer engagements, RFIs, and technical proposals Provide expert‑level IP support to customers, including architecture clarification, feature customization Work cross‑functionally with design, verification, layout, and silicon validation teams to ensure architectural intent is correctly implemented Review and guide architecture specifications, design reviews, and technical documentation Influence product and technology roadmap planning by identifying future standards, protocol evolution, and customer-driven requirements Demonstrate strong communication, accountability, and technical ownership across internal and external interactions

Requirements

• M.S. degree in Electrical Engineering, Computer Engineering, or related field
• Minimum 15 years of industry experience in memory interface PHY, high‑speed IO, or related domains
• Strong background in memory interface PHYs, JEDEC standards, and protocols
• Proven ability to own customer‑facing technical engagements and drive issues to closure
• Excellent written and verbal communication skills

Responsibilities

• Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations
• Drive architecture decisions aligned with JEDEC standards, protocols, and compliance requirements
• Good understanding of PHY/IO circuit architecture including TX/RX, clocking, termination, power delivery, and signal integrity trade‑offs
• Act as a customer‑facing technical architect during pre‑sales, evaluations, and post‑delivery support, clearly articulating architecture choices and trade‑offs
• Collaborate closely with Sales, Marketing, and Program teams to support customer engagements, RFIs, and technical proposals
• Provide expert‑level IP support to customers, including architecture clarification, feature customization
• Work cross‑functionally with design, verification, layout, and silicon validation teams to ensure architectural intent is correctly implemented
• Review and guide architecture specifications, design reviews, and technical documentation
• Influence product and technology roadmap planning by identifying future standards, protocol evolution, and customer-driven requirements
• Demonstrate strong communication, accountability, and technical ownership across internal and external interactions

Benefits

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees