Design Engineering Architect
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About The Position
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The position involves reviewing the High-level architecture specification (HAS) for the ARM A-class Core and System IP, which includes Class-A CPU, CMN, GIC, and SMMU. The role requires defining the system architecture for integrating the Aspen CSS with the System Chiplet and NPU chiplet. Additionally, the candidate will compare Risc-V CPU and ARM CPU architectures. Collaboration with the design team is essential, particularly with the design lead of the HW4 SOC, which is the most recent ADAS project from Tesla. In-person discussions with the design team, including the MAS, will be beneficial. The design from the EDI team must differ from the Tesla SoC, necessitating communication between teams. The candidate will also review the MAS to ensure consistency with the HAS, as modifications may be required based on the design team's guidance. Furthermore, the role involves working with the performance team to define performance expectations for the ARM A-class Core and System IP.
