Design Engineer

Broadcom • San Jose, CA

9d • $120,000 - $192,000

About The Position

In this position you will use your physical design expertise to do physical implementation of challenging designs in 2nm/3nm/5nm technology nodes . The person should have hands on experience on netlist->gds implementation of multimillion gates including but not limited to floorplanning place and route, STA, physical verification(LVS?DRC/ANT/ERC). Work closely with designers and must be able to write TCL script to perform custom/semi-custom standard cells placements/clock tree adjustments/routing to achieve design specs. Good timing analysis and CTS knowledge is required. Full chip assembly and experience on spice simulation is a plus.

Requirements

• MSEE/MSCS 6+ years (BSEE/BSCS 8+ years)
• Expertise in Cadence Innovus/Atop physical design tools
• Experience on Calibre LVS/DRC
• Work closely with RTL & DFT designers
• Strong TCL/Python scripting knowledge required, Perl is a plus.
• Good debug skill and be able to work around issues
• Tape out experience must be a good team player

Nice To Haves

• Hands on experience on hierarchical top level floorplanning, IO ring design, place and route, clock tree building, STA is preferable.

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees