Design Engineer

Broadcom•Fort Collins, CO

46d

About The Position

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production. This Design Engineering position focuses on the physical implementation of high-performance ASICs, providing hands-on experience with the latest 3 nm and smaller process nodes. The role offers exposure to advanced design methodologies and close collaboration with senior engineers across multiple disciplines to deliver industry-leading silicon solutions.

Requirements

Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals.
Familiarity with ASIC physical design concepts such as placement, routing, and timing.
Strong analytical and debugging skills, with the ability to quickly learn new tools and flows.
Proficiency in UNIX/Linux environments.
Working knowledge of TCL; familiarity with Python or Perl preferred.
Excellent communication, collaboration, and problem-solving abilities.
Ability to work effectively with cross-functional and global teams.
Highly motivated, detail-oriented, and eager to learn in a fast-paced R&D environment.
Demonstrates strong engineering judgment, ownership, and accountability.
Bachelor’s degree in Electrical or Electronics Engineering, or Master’s degree in Electrical or Electronics Engineering.

Nice To Haves

Exposure to EDA tools such as Cadence Innovus, Synopsys ICC2, or PrimeTime is a plus.

Responsibilities

Contribute to the physical design implementation of large-scale ASICs (multi-hundred-million gate complexity).
Support key design activities including floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification (DRC/LVS).
Collaborate with cross-functional teams on block-level integration, timing analysis, and design signoff.
Utilize both commercial and in-house EDA tools for design, implementation, and verification.
Contribute to design flow improvements, automation, and deep sub-micron methodology development.
Assist in timing analysis, power planning, IR/EM checks, and post-route optimization.
Gain exposure to the complete ASIC design cycle — from RTL to GDSII and silicon bring-up.
Interface with customers and internal stakeholders to support technical discussions and design reviews.