Design Engineer Lead
About The Position
There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. A successful candidate will join a team designing and developing Lattice Foundation IP at Penang to help strengthen broad technical ownership of IP deliverables. The candidate will lead research, design and development of Lattice Foundation IP and/or FPGA primitives, as well as helping to refine Product Life Cycle e.g. planning, development & testing processes. The candidate is expected to play a lead role in cross-functional teams to plan and coordinate Lattice Foundation IP release cycle including requirement analysis, feature scoping, development, testing and validation.
Requirements
- Bachelors, Masters or better in Computer Science, Computer Engineering, Electrical Engineering, or related fields with 12+ years of experience in FPGA IP and/or EDA tools development.
- Strong communication skills
- Knowledge or experience in FPGA architecture and FPGA software tools
- Hands-on experience in complex end-to-end FPGA RTL design, testbench development, logic verification, timing closure across multi-clock domains and systematic root-cause debugging of functional and/or timing issues.
Nice To Haves
- Expert in multi-domain FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features.
- Experience in safety related SoC and/or FPGA Soft IP development and verification with proven ability to generate audit ready Functional Safety evidence in compliance with IEC 61508, ISO 26262 or other safety standards is a strong plus.
Responsibilities
- Lead research, design and development of Lattice Foundation IP and/or FPGA primitives
- Refine Product Life Cycle e.g. planning, development & testing processes
- Play a lead role in cross-functional teams to plan and coordinate Lattice Foundation IP release cycle including requirement analysis, feature scoping, development, testing and validation.
Benefits
- The base pay for this role is between $175,000 to $219,000 per year.
- In addition to base salary, we offer an incentive plan bonus, and new hire equity for a competitive total compensation package.
- Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.
- Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Number of Employees
501-1,000 employees
