Design Engineer - Chip Floorplanner

Broadcom-posted 4 days ago
Full-time • Mid Level
Fort Collins, CO
5,001-10,000 employees
Resume
Match Score
Upload and Match ResumeTrack Jobs with Teal

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This position offers the opportunity to work on high-performance SoC designs operating at speeds exceeding 1 GHz, from concept through production. This Floorplanning Engineer role focuses on chip-level physical architecture and integration for advanced ASICs in deep sub-micron technologies. The position provides hands-on experience with the latest 3 nm and smaller process nodes, defining and optimizing the overall die layout, including partitioning, hierarchy, and placement of major functional blocks, memories, and I/O structures for AI, computing, and networking SoCs.

  • Define and optimize top-level floorplan architecture, including die size estimation, hierarchy definition, and partitioning.
  • Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization.
  • Collaborate closely with RTL, timing, and packaging teams to balance performance, power, and area (PPA) targets.
  • Lead top-level timing closure, congestion analysis, and ECO implementation to ensure clean tapeout readiness.
  • Coordinate with block owners and integration teams for smooth block-level to top-level convergence.
  • Support cross-functional design integration, providing guidance and technical support to internal and external partners.
  • Apply a deep understanding of block PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff-quality results.
  • Contribute to design flow automation and methodology development for advanced process technologies.
  • Strong foundation in VLSI design principles and ASIC physical design fundamentals.
  • In-depth experience with floorplanning, die partitioning, and hierarchical design.
  • Working knowledge of PLLs, clock networks, power delivery, and timing-critical structures.
  • Familiarity with physical verification, DRC/LVS, and congestion/power analysis.
  • Proven ability to drive PPA optimization through innovative layout and planning strategies.
  • Strong experience with TCL scripting and Linux environments is required.
  • Excellent communication, organizational, and problem-solving skills.
  • Ability to work effectively with customers and cross-functional teams across global sites and time zones.
  • Skilled at organizing and presenting large data sets, managing multiple priorities efficiently.
  • Exercises independent judgment and strong engineering insight in defining methods, techniques, and evaluation criteria.
  • Provides technical leadership, mentors others, and leads execution of new initiatives.
  • BS in Electrical or Computer Engineering with 12+ years of relevant experience, or MS in Electrical or Computer Engineering with 10+ years of relevant experience.
  • Proficiency in Python, Perl, or Ruby is preferred.
  • Experience with Cadence or equivalent physical design tools is highly desirable.
  • Medical, dental and vision plans
  • 401(K) participation including company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • company paid holidays
  • paid sick leave and vacation time
Track Jobs with Teal

Job Search Resources

•
AI Resume Builder
•
ASIC Design Engineer Resume Examples
•
Cover Letter Examples

Tools

Career Hubs

Guides

Company

© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service