Design Engineer – AI SoC Development

Intel Corporation • Folsom, CA

1d • Hybrid

About The Position

Intel's AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware. Position Overview As an RTL Design Engineer, you will develop logic design, register transfer level (RTL) coding, and simulation for SoC designs while integrating IP blocks and subsystems into full chip SoC or discrete component designs. You'll participate in defining architecture and microarchitecture features of the blocks being designed and perform quality checks across various logic design aspects ranging from RTL to timing/power convergence. You will apply various strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation. Working closely with verification teams, you'll review verification plans and implementation to ensure design features are verified correctly, resolving and implementing corrective measures for failing RTL tests. Additionally, you'll follow secure development practices to address security threat models and security objectives within the design, work with IP providers to integrate and validate IPs at the SoC level, and drive quality assurance compliance for smooth IP/SoC handoff.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
• 4+ years of experience in/with: RTL design and implementation for ASIC/SoC development
• Proficiency in Verilog/SystemVerilog for RTL coding and design
• Experience with synthesis tools and timing closure methodologies
• Ability to work in a dynamic environment and adapt to changing requirements
• Strong problem-solving skills, collaborative mindset, and eagerness to learn

Nice To Haves

• Understanding of clock domain crossings, power optimization, and timing closure
• Exposure to SoC system integration and CPU subsystem design
• Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
• Knowledge of high-speed and low-power design techniques
• Experience with static timing analysis (STA) tools and methodologies
• Hands-on experience with formal verification tools and techniques
• Basic scripting skills (Python, TCL, etc.) for automation
• Experience with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools

Responsibilities

• Contribute to evaluation of architectural trade-offs considering features, performance, and system constraints
• Implement RTL in Verilog/SystemVerilog based on defined micro-architecture; integrate IP blocks at top level and ensure synthesis- and timing-clean design
• Work closely with verification teams to achieve full coverage and robust validation
• Develop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks
• Support silicon bring-up and post-silicon validation activities, including debug and performance analysis
• Collaborate with senior engineers to adopt best practices and improve design methodologies

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.
• Find more information about all of our Amazing Benefits here: https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees