Design Verification Engineer responsible for verifying TSMC's product like ARM processor based SOC and memory subsystem Testchips. Develop verification methodology and implement testbench components using System Verilog and UVM. Develop comprehensive test plan and implement test cases to verify different Testchips. Work closely with Design and DFT teams to develop and verify various functional/DFT Tests. Perform Low Power Design Verification using UPF. Write functional cover groups and cover points for coverage closure. Perform RTL code coverage, System Verilog Assertion coverage, System Verilog functional coverage. Developing, running and improving regression suite to meet coverage goal. Conducting verification review for RTL/Netlist freeze and Tape-out. Drive and adopt new verification methodologies and flows for efficiency improvements.