Summer 2026 - Design DFT/DV Engineer Intern (7410)

TSMC • San Jose, CA

21h • $38 - $45

About The Position

Join our dynamic DFT and Verification team at TSMC, where you will play a pivotal role in the development and validation of cutting-edge logic test chips. These chips are instrumental for pioneering yield learning in advanced process nodes and pushing the boundaries of advanced packaging technologies. This internship offers a unique opportunity to tackle complex, real-world challenges at the forefront of semiconductor innovation.

This program is designed for exceptional students currently pursuing a Master’s or Ph.D. degree in Electrical or Computer Engineering, with an expected graduation date in 2026 or 2027. The internship will commence in Summer 2026 and continue through Fall 2026, providing a substantial period for impactful contributions and learning.

Requirements

• Currently enrolled in a Master’s or Ph.D. program in Electrical Engineering, Computer Engineering, or a closely related field, with an expected graduation date in 2026 or 2027.
• Demonstrated strong problem-solving abilities and proficiency in programming languages such as Verilog, Python, and TCL.
• Practical experience utilizing Python for building machine learning models and data analysis.
• Solid fundamental knowledge of Design-for-Test (DFT) techniques, including ATPG, simulation, logic diagnosis, and Scan compression.

Nice To Haves

• Familiarity with industry-standard EDA tools such as Synopsys DFT Compiler, Tetramax, and VCS.
• Research or project experience in defect analysis, fault diagnosis, or testing methodologies for advanced semiconductor technologies (e.g., 3D ICs, chiplet interconnects, novel memory architectures).
• Exposure to advanced packaging concepts and their implications for test strategies.
• Experience with SystemVerilog (OOP) and advanced verification methodologies.

Responsibilities

• Advanced DFT/DV Pattern Simulation & Analysis: Perform block and top-level DFT/DV pattern simulations. Develop and utilize TCL/Verilog monitors to generate comprehensive run-time information, facilitating precise tracking of simulation progress and performance.
• Automated Defect Insertion & Failure Diagnosis: Implement and execute methodologies for inserting predefined static and dynamic defects/fails. Run simulations to collect detailed fail logs, applying automated clustering techniques to efficiently identify and diagnose the root cause of failures.
• ATPG & Test Model Explorer Development: Contribute to the development and maintenance of ATPG and test model (STIL/CTL/BSDL/WGL) explorers. This includes modifying and updating test files in response to evolving design changes and specifications.
• Machine Learning for Simulation Diagnosis: Leverage machine learning and data mining techniques to enhance simulation failure diagnosis, particularly in the context of advanced process nodes. This involves applying cutting-edge analytical methods to complex data sets.

What This Job Offers

• Career Level: Intern
• Education Level: Ph.D. or professional degree