DDR IP Verification Engineer

Microsoft • Raleigh, NC

4d

About The Position

Own or lead verification of one or more aspects/features of a memory controller Intellectual Property (IP) and/or Double Data Rate (DDR) subsystem integration with Physical Layer (PHY) Learn about the design and interact with partner teams to define verification strategies and test plans Develop verification environments and run and debug simulations to drive quality Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals Innovate to improve verification efficiency through methodologies or tools Apply industry leading generative AI solutions to verification work Coach and mentor others in your areas of expertise

Requirements

• Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.
• OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ year(s) technical engineering experience or internship experience.
• OR Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, Information Technology, or related field.
• 2+ years of pre-silicon subsystem or IP verification experience.
• 1+ years of DDR subsystem verification experience.
• Good experience in verifying memory controller, DDR PHY, and/or at DDR sub-system level including integration verification of memory controller IP with DDR PHY and Electronic Design Automation (EDA) vendor sourced Dual In-line Memory Module (DIMM) Verification IP (VIP)
• Deep understanding of JEDEC spec including mode registers, timing parameters, refresh operations, initialization, calibration, training, power management, and error handling.
• Experience with verification for a full product cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff.
• Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking.
• Aptitude for writing scripts/software with industry standard languages like Python.
• Experience applying generative AI to day-to-day tasks.

Responsibilities

• Own or lead verification of one or more aspects/features of a memory controller Intellectual Property (IP) and/or Double Data Rate (DDR) subsystem integration with Physical Layer (PHY)
• Learn about the design and interact with partner teams to define verification strategies and test plans
• Develop verification environments and run and debug simulations to drive quality
• Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
• Innovate to improve verification efficiency through methodologies or tools
• Apply industry leading generative AI solutions to verification work
• Coach and mentor others in your areas of expertise

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level
• Number of Employees: 5,001-10,000 employees