DDR Design Engineer

Apple-posted 2 months ago
Austin, TX
5,001-10,000 employees
Computer and Electronic Product Manufacturing
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At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented DDR Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. You will join the DDR PHY design team. We provide best-in-class PHY designs for high-performance, low power applications. As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.

  • Performing concept studies and provide direction in terms of performance, gate count and power for various digital designs.
  • Writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers.
  • Providing high-quality RTL description, including assertions, for the design.
  • Using formal tools and static checkers to guarantee RTL quality.
  • Supporting design verification to ensure bug-free first silicon.
  • Driving functional and code coverage as well as timing closure for your designs.
  • Supporting silicon bring-up, performance and power characterization.
  • RTL design using Verilog or SystemVerilog, assertion writing.
  • Design of state machines, data paths, arbitration and clock domain crossing logic.
  • Logic synthesis, timing constraints.
  • Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL.
  • Unified Power Format for simulation, synthesis and electrical rule checking.
  • Equivalence checking.
  • Experience in RTL design using Verilog or SystemVerilog.
  • Strong understanding of digital design concepts including state machines, data paths, and clock domain crossing logic.
  • Experience with logic synthesis and timing constraints.
  • Familiarity with Design For Test (DFT) concepts and writing DFT friendly RTL.
  • Knowledge of Unified Power Format for simulation and synthesis.
  • Experience with formal tools and static checkers.
  • Prior experience in DDR PHY design.
  • Experience in a mixed-signal environment.
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