Data Cache & Coherent Interconnect Architect/Engineer

Qualcomm • Santa Clara, CA

196d • $154,000 - $252,800 • Remote

About The Position

Qualcomm, a global leader in mobile and high-performance computing, is building a new team to develop a next-generation processor. We are seeking talented engineers and architects to join a dedicated group focused on designing and implementing Data Caches and a Coherent Interconnect for cutting-edge SoCs. As a key contributor, you will be responsible for architecture definition, performance modeling, analysis, and RTL implementation of cache and interconnect subsystems. This is a unique opportunity to work on a high-impact project in a collaborative and innovative environment.

Requirements

• Strong background in processor architecture and micro-architecture.
• Hands-on experience with data caches and coherent interconnects.
• Familiarity with cache coherence protocols (e.g., CHI, ACE, or equivalent).
• Proficiency in C/C++ and/or Verilog/SystemVerilog.
• Experience in IP development and performance analysis.
• Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 4+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience, OR Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field and 3+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience, OR PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field and 2+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• 2+ years of experience with high-performance microprocessor design.

Nice To Haves

• Prior experience with CHI protocol or similar.
• Exposure to SoC integration and system-level performance modeling.
• Strong analytical and debugging skills.

Responsibilities

• Architect and design high-performance data cache subsystems and coherent interconnects.
• Develop performance models and analyze trade-offs in power, area, and latency.
• Collaborate with cross-functional teams including architecture, RTL, verification, and software.
• Contribute to the development of new IP blocks and integration into SoC platforms.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants.
• Highly competitive benefits package designed to support your success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Master's degree
• Number of Employees: 5,001-10,000 employees