Qualcomm-posted 5 months ago
$154,000 - $252,800/Yr
Full-time • Mid Level
San Diego, CA
5,001-10,000 employees

Qualcomm, a global leader in mobile and high-performance computing, is building a new team to develop a next-generation processor. We are seeking talented engineers and architects to join a dedicated group focused on designing and implementing Data Caches and a Coherent Interconnect for cutting-edge SoCs. As a key contributor, you will be responsible for architecture definition, performance modeling, analysis, and RTL implementation of cache and interconnect subsystems. This is a unique opportunity to work on a high-impact project in a collaborative and innovative environment.

  • Architect and design high-performance data cache subsystems and coherent interconnects.
  • Develop performance models and analyze trade-offs in power, area, and latency.
  • Collaborate with cross-functional teams including architecture, RTL, verification, and software.
  • Contribute to the development of new IP blocks and integration into SoC platforms.
  • Strong background in processor architecture and micro-architecture.
  • Hands-on experience with data caches and coherent interconnects.
  • Familiarity with cache coherence protocols (e.g., CHI, ACE, or equivalent).
  • Proficiency in C/C++ and/or Verilog/SystemVerilog.
  • Experience in IP development and performance analysis.
  • 2+ years of experience with high-performance microprocessor design.
  • Prior experience with CHI protocol or similar.
  • Exposure to SoC integration and system-level performance modeling.
  • Strong analytical and debugging skills.
  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Highly competitive benefits package designed to support your success at work, at home, and at play.
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