DFx Engineer

Samsung • Austin, TX

124d • $144,345 - $223,735 • Onsite

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! As a seasoned DFx engineer, you will be involved across the entire spectrum of activities all the way from defining the DFT scan architecture through implementation and culminating in pattern generation including silicon debug. You will be working on IP-level projects (GPU, system interconnect) in bleeding-edge processes that continually drive high test-coverage requirements. This position is local to Austin, TX only.

Requirements

• 10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD.
• 10+ years of DFx expertise encompassing multiple tapeouts for digital IP (CPU / GPU) and/or SOC projects.
• Demonstrated ability to architect DFT solutions from scratch on at least 1 project.
• Create detailed specifications that can be used as a blueprint for implementation.
• Detailed understanding of test-coverage requirements across various scan modes.
• Strong familiarity with RTL coding & STA with working knowledge of Physical Design.
• Familiarity with multi-voltage and multi-clocking domain implementation is a plus.
• Strong post-silicon experience as it relates to debugging silicon behavior and test-escape issues.
• Ability to solve difficult problems with creative solutions or analysis.
• Crisp written and oral communication skills including working with global stakeholders.
• Ability to thrive in a fast-paced environment with yearly project tapeouts.

Nice To Haves

• Exposure to advanced approaches including hierarchical DFT and streaming fabric.

Responsibilities

• Define the DFT scan architecture and implement it, culminating in pattern generation and silicon debug.
• Work on IP-level projects (GPU, system interconnect) in bleeding-edge processes.
• Understand SOC requirements and project milestones to help define a DFT architecture that balances coverage, test-time, and execution.
• Create a detailed implementation spec documenting the architecture including SOC-level interface, clock design, and support of various test/debug modes.
• Close on the spec with stakeholders including DFX / RTL / SOC / STA / PD teams.
• Implement DFT scan: RTL creation, LINT, timing-constraints, ATPG, and simulation.
• Benchmark test-coverage and test-time to ensure they meet expectations.
• Drive towards continuing DFX excellence: improving test-coverage, minimizing test-time, and exploring tools/methods that improve execution efficiency.
• Build strong collaboration with SOC and Product/Test Engineering teams to resolve silicon issues including test-escapes and yield loss.

Benefits

• Medical, dental, vision, life insurance.
• 401(k).
• Free onsite lunch.
• Employee purchase program.
• Tuition assistance (after 6 months).
• Paid time off.
• Student loan program.
• Wellness incentives.
• MBO bonus compensation based on performance.
• Eligibility for long term incentive plan and relocation.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Merchant Wholesalers, Durable Goods
• Education Level: Bachelor's degree