Cryptography & Side Channel Security Expert

Advanced Micro Devices, IncAustin, TX
Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. AMD’s Product Security Office (PSO) is seeking a cryptography and side‑channel security expert to help ensure AMD platforms deliver state‑of‑the‑art cryptographic security across silicon, firmware, and system implementations. The role centers on evaluating cryptographic implementations and executing side‑channel and fault‑injection assessments, then translating findings into robust, practical countermeasures that fit real product constraints (performance/area/power/schedule). You will operate in a highly cross‑functional environment—working with security engineering, silicon/RTL teams, firmware teams, validation, and platform stakeholders—to identify leakage, validate mitigations, and raise the security bar across AMD roadmaps. The ideal candidate should be passionate about cryptographic engineering and be able to ensure that high impact vulnerabilities are found early (pre‑silicon where possible), clearly characterize them, and close with mitigations that are verifiable and scalable. The candidate should be able to not only propose countermeasures, but also validate them against realistic attacker models using repeatable test methodology. The candidate should be able to enable cross‑team partners adopt actionable guidance, improving security posture without derailing product constraints.

Requirements

  • Experience with microarchitecture/RTL security considerations for cryptographic IP and/or familiarity with secure hardware design concepts.
  • Familiarity with SCA toolchains and lab workflows (e.g., measurement setups, instrumentation, automation) and common platforms used in practice (like ChipWhisperer / Keysight Inspector toolchains).
  • Exposure to broader hardware security testing domains within a secure development lifecycle context.
  • Master’s or PhD degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent.

Responsibilities

  • Assess security properties of cryptographic designs and implementations (hardware and firmware), including algorithm/implementation tradeoffs across area, performance, and security.
  • Evaluate and harden cryptographic subsystems used in AMD platforms; provide clear security guidance and recommendations to diverse engineering stakeholders.
  • Contribute to cryptographic roadmap and use‑case exploration (including modern and emerging algorithms) and produce technical reports to drive implementation decisions.
  • Perform side‑channel vulnerability discovery, including power and electromagnetic (EM) measurements, leakage detection, and attack development against cryptographic targets.
  • Execute and/or develop evaluation methodologies spanning SPA/DPA/CPA, EM analysis, and fault analysis (e.g., DFA) to characterize leakage and exploitability.
  • Design, recommend, and validate countermeasures (e.g., masking/hiding strategies, implementation hardening, and testable mitigation approaches) and confirm resilience against attacks.
  • Conduct SCA on targets across pre‑silicon environments (e.g., RTL/isolated engines, simulation‑based or FPGA‑based setups) and post‑silicon AMD platforms.
  • Create/extend test environments to enable repeatable security evaluations, including triggering, trace collection, and automation for large measurement setups.
  • Partner across the silicon lifecycle to drive “shift‑left” security thinking and ensure security testing includes side‑channel analysis and fault injection where appropriate.
  • Communicate complex cryptographic and physical‑attack findings clearly to both technical and non‑specialist stakeholders.
  • Represent AMD security work in appropriate internal/external forums and foster relationships with experts and academic collaborators (as aligned with PSO research/engagement goals).
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