CPU Physical Design - Low Power Signoff Engineer

Qualcomm • San Diego, CA

152d • $148,300 - $222,500 • Remote

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units.

Requirements

• 2-10 years experience in Physical Design and timing signoff for high speed cores.
• Good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.
• Master's/Bachelor's Degree in Electrical/Electronics science engineering with at least 2+ years of experience in IC design.
• Experience in leading block level or chip level Physical Design, STA and PDN activities.
• Work independently in the areas of RTL to GDSII implementation.
• Ability to collaborate and resolve issues regarding constraints validation, verification, STA, Physical design, etc.
• Knowledge of low power flow (power gating, multi-Vt flow, power supply management, etc.).
• Circuit level comprehension of time critical paths in the design.
• Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM, etc.).
• Tcl/Perl scripting skills.
• Strong problem-solving skills.
• 2+ years Hardware Engineering experience or related work experience.
• 2+ years experience with PNR flow and CLP/FV runs in latest tech nodes (e.g., 4nm/5nm/7nm/10nm).
• Good hands-on experience on signoff domains- LEC/CLP flows, Synthesis, Floorplanning, PNR and STA flows.
• Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc.
• Good knowledge on Unix/Linux - Perl/TCL fundamentals/scripting.

Responsibilities

• Complete ownership on Conformal Low Power and Formal Verification signoff for hier and flat CPU Subsystem on latest nodes.
• Handle CLP and FV signoff from synthesis to PNR exit.
• Ensure signoff knowledge is mandatory (STA, Power analysis, FV, low power verification, PV, etc.).
• Demonstrate quick learning with good analytical and problem-solving skills.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants.
• Highly competitive benefits package designed to support success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees