CPU Physical Design Engineer (San Diego)

Qualcomm • San Diego, CA

1d

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units.
As a CPU Physical Design Engineer, you will work with microarchitecture and RTL design team to implement the designs meeting aggressive power, area and performance goals using industry standard tools/flows.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Nice To Haves

• Knowledge of CPU microarchitecture.
• Experience in deep submicron process technology nodes is strongly preferred.
• Knowledge of library cells and optimizations.
• Solid understanding industry standard tools for synthesis, place & route and tapeout flows.
• Experience with Synthesis, place and route and signoff timing/power analysis.
• Knowledge of high performance and low power implementation methods
• Knowledge of CPU microarchitecture, logic design and circuits

Responsibilities

• Work with CPU microarchitecture team to understand specifications and design trade offs in pipeline and structure sizing.
• Perform feasibilities to validate implementability, area, timing and power.
• Synthesize the Verilog RTL into gate level designs and perform optimizations.
• Perform SynthPlace & Route on the designs using industry standard tools and deliver GDS.
• Optimize the design at various stages from RTL to GDS to meet timing, power and area goals.
• Validate the designs for functional and electrical robustness.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level