CPU Micro-Architect

Samsung Electronics•Austin, TX

22h

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! We are seeking a highly experienced CPU Micro-Architect to join our team at Samsung SARC/ACL. As a CPU Micro-Architect, you will be responsible for designing and optimizing high-performance CPU microarchitectures for mobile, data center, and other applications. You will develop and implement innovative microarchitecture techniques, analyze performance, and optimize SoC designs. You design and optimize high-performance CPU microarchitectures for mobile and other applications You perform quantitative analysis of key mobile benchmarks and correlate with hardware performance monitoring unit (PMU) stats You develop and implement innovative microarchitecture techniques such as pipelining, caching, prefetching, and branch prediction You collaborate with cross-functional teams to develop and integrate system-on-chip (SoC) designs You analyze and optimize CPU performance using top-down microarchitecture analysis methods You extract and assess key microarchitecture ideas from open literature and apply them to our designs You write RTL code (Verilog or SV) and C/C++/Python scripts for performance evaluation of microarchitecture techniques

Requirements

15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a Ph.D.
Strong fundamentals in key computer architecture concepts, such as virtual aliasing, pipelining, cache hierarchies, coherency, memory subsystem, etc.
Deep knowledge in high-performance OoO CPU microarchitecture and SOTA optimization techniques in key areas such as pipelining, interlock, caching, prefetching, branch prediction, cache/TLB hierarchy and their PPA implications
Ability to perform quantitative analysis of key mobile benchmarks such as Geekbench6 and SPECCPU17 and correlation with HW PMU stats (cache misses, TLB misses, pipeline stalls, etc.)
Extensive programming experience with RTL code (Verilog or SV), and writing C/C++/Python scripts, for performance evaluation of uarch techniques
Working experience with top-down microarchitecture analysis method (based on PMU stats)
Ability to extract and assess key uarch ideas in open literature
Strong communication and collaboration skills, with the ability to work effectively in a cross-functional team environment

Nice To Haves

Actual RTL implementation experience on high-performance OoO processors
Knowledge of system-on-chip (SoC) design and integration
Experience with machine learning and AI accelerators
Working experience of Armv8/v9 ISA and extensions or equivalent (such as x86 and RISCV), particularly in the areas of vector/AI/security/memory safety features (such as Realms, memory tag extension) and their use cases

Responsibilities

design and optimize high-performance CPU microarchitectures for mobile and other applications
perform quantitative analysis of key mobile benchmarks and correlate with hardware performance monitoring unit (PMU) stats
develop and implement innovative microarchitecture techniques such as pipelining, caching, prefetching, and branch prediction
collaborate with cross-functional teams to develop and integrate system-on-chip (SoC) designs
analyze and optimize CPU performance using top-down microarchitecture analysis methods
extract and assess key microarchitecture ideas from open literature and apply them to our designs
write RTL code (Verilog or SV) and C/C++/Python scripts for performance evaluation of microarchitecture techniques