CPU Micro-architect/RTL Designer (Multiple Locations)

Qualcomm-posted 5 months ago
$139,000 - $234,500/Yr
Remote • Santa Clara, CA
5,001-10,000 employees
Computer and Electronic Product Manufacturing
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Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle.

  • Performance exploration. Explore high performance strategies working with the CPU modeling team.
  • Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.
  • RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.
  • Functional verification support. Help the design verification team execute on the functional verification strategy.
  • Performance verification support. Help verify that the RTL design meets the performance goals.
  • Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power.
  • Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems.
  • Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools.
  • Knowledge of logic design principles along with timing and power implications.
  • Understanding of low power microarchitecture techniques.
  • Understanding of high performance techniques and trade-offs in a CPU microarchitecture.
  • Experience using a scripting language such as Perl or Python.
  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Highly competitive benefits package designed to support success at work, at home, and at play.
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