CPU Memory Subsystem Design Manager

Google • Mountain View, CA

275d • $227,000 - $320,000

About The Position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including integration into the goal-oriented System on a Chips (SoC). You will lead and manage a front-end design team, collaborate with members of architecture, software, verification, power, DFT, physical design teams to define the microarchitecture and schedule in delivering high quality RTL that meets project goals. You will help your team grow and solve technical problems with innovative micro-architecture and practical logic solutions. You will be responsible for evaluating and deciding on the best design options with complexity, performance, power and area and schedule in mind.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in CPU memory subsystem design.
• 10 years of experience in high-performance CPU, cache subsystem or AI accelerator logic/RTL design including microarchitecture definition and PPA optimizations.
• 6 years of experience leading and managing teams for modern processor subsystems with high speed, and lower power design.

Nice To Haves

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or related field, or equivalent practical experience.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, UPF, and Low Power Optimization/Estimation).
• Experience with mobile CPU subsystem and SoC architecture/integration.
• Experience with ARM Instruction Set Architecture.

Responsibilities

• Lead and manage a team of design engineers working on CPU, cache subsystem, or AI accelerator design and integration into SoC, emphasizing on microarchitecture and RTL design for the next generation CPU subsystem.
• Review/propose performance enhancing microarchitecture features, and work with Software, Architect and Performance teams for trade-off studies. Communicate the pros and cons of microarchitecture enhancements.
• Deliver with plans on achieving project milestones and goals, towards a design that meets production quality on schedule.
• Work with the Verification team to ensure production of quality designs, the physical design and power teams to meet frequency, power, and area goals.
• Focus on cache subsystem design, e.g. L1(LSU), L2/L3 private and d caches, and optimizations with other parts of CPU to deliver the best Power Performance Area (PPA).

Benefits

• Bonus
• Equity
• Health benefits

What This Job Offers

• Job Type: Full-time
• Industry: Web Search Portals, Libraries, Archives, and Other Information Services
• Education Level: Bachelor's degree