This job is no longer available
There are still lots of open positions. Let's find the one that's right for you.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with Micro-architects to define memory subsystem and perform feasibility using Genus, Innovus, and Primetime tools. Evaluate and incorporate various macro/compiler IP’s and storage structures like flop/latch-arrays to make area/frequency/performance/power tradeoffs. Enhance the design and balance the pipeline stages by studying RTL datapath and control flow using Verdi and Power Artist. Drive RTL-to-GDS flow through Genus, DCG synthesis tools and perform place-and-route using Innovus, ICC2 tools. Perform gate-dept reduction, Verilog RTL recoding and employ physical design techniques like bounding, path-groups, structured and activity driven placement, custom clocking and routing. Work with cross-functional engineering team to implement and validate physical design on the aspects of timing using Primetime, reliability by measuring SIGEM, EMIR and testability by implementing scan ATPG and MBIST and power. Utilize microprocessor architecture and work on different sub-blocks like front-end fetch, dispatch, rename, integer and floating point execution with load-store sub-systems, to improve the current design and enhance future products. Implement timing, power saving techniques and logic design principles to improve efficiency of execution and provide timely design feedback to build better mobile products.
