CPU Debug and Power Management Verification Engineer

Apple • Beaverton, OR

1d

About The Position

At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. The company is committed to innovation and leaving the world better than they found it. This highly visible role is at the center of a chip design effort, collaborating with all disciplines, and has a critical impact on delivering functional products to millions of customers quickly. The position is for a highly motivated Design Verification Engineer to join the silicon engineering team, focusing on auxiliary features of a high-performance ARM-based CPU. These features include Power Management, Clock Control, Debug Infrastructure, Resets, and Special-Purpose Registers, encompassing both ARM-standard capabilities and Apple-specific innovations. The engineer will work across the entire product lifecycle, from pre-silicon test planning to supporting post-silicon bring-up and debug. This cross-functional role bridges CPU and SoC teams and is critical for delivering robust, low-power, high-performance CPU designs.

Requirements

• Minimum BS and 10+ years of relevant industry experience
• Programming skills in Perl/Python or SystemVerilog

Nice To Haves

• Experience in processor or power management architecture and verification
• Experience with system fabric protocols such as AXI
• In-depth knowledge in design verification environments like random constraint verification and/or UVM base testbenches
• Experience in system Verilog assertions or silicon bringup or UPF and low power simulation
• Experience in processor debug features including hardware trace is a plus
• Experience with advanced verification techniques such as formal verification is a plus
• Advanced programming skills such as object orientated programming or CPU assembly language is a plus
• Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort
• Be able to create and follow detailed work schedules and work independently on the verification efforts for a block/area of the design

Responsibilities

• Work closely with architecture and RTL designers on verifying the functionality correctness of CPU Power Management, clock control, and debug logic
• Develop and execute test plans and schedules
• Write and debug tests in Assembly, SystemVerilog, SVA, C++, and scripting languages to validate functionality in simulation, emulation, and FPGA environments
• Build and maintain verification infrastructure, including checkers, transactors, and coverage monitors.
• Analyze functional coverage to ensure test plan completeness
• Identify, root-cause, and document design issues and collaborate with RTL teams to drive fixes
• Support SoC-level debug for clock and power integration issues
• Work with silicon bring-up teams to develop tests and debug issues across emulation, FPGA, and silicon. Contribute to post-silicon debug, using waveform and trace tools to diagnose complex system issues.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 5,001-10,000 employees