You will be a member of the ACE UC CPU Design Automation CAD team. You will be responsible for: Develop and to architect new tools and flows for RTL to physical design as well as enhance existing flows for better efficiency and robustness. Develop and maintain RTL to layout design infra-structure, including full internal cloud management and optimization, permissions and license management. Compute and storage forecast and management. Develop and support flows including a flow control manager which is responsible for running physical collateral through the necessary stages for backend integration. Use ML and other techniques to analyze the content of the BE databases for better storage and faster access. Analysis of compute and memory usage for the aggregate jobs of the FE and BE flows with the goal of more efficient and effective compute use. Provide and support indicators that quickly measure compute, memory and disk resources for efficiencies and sends alerts when key resources are highly utilized. Enablement and development of the Front-End (RTL, Verification) and back end (BE) databases and flows for ACE CPU physical design collateral. Includes the setup and support of the user environment for all design tools and flows. Strong knowledge of cloud management tools Familiarity with Data structures and Algorithms You will work closely with the FE and BE design engineers as well as engineering compute (EC) for enablement and support of the BE environment.