AMD-posted 3 months ago
Austin, TX
Computer and Electronic Product Manufacturing

At AMD, we care deeply about transforming lives with our technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming, and embedded systems. As a member of the Cores DFT Team, the successful candidate will own the ATPG responsibilities for the next generation of AMD high-performance cores. As a senior member of the DFT team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

  • Interact with PD and Front End Integration team for Scan Insertion
  • Interface with the design teams to ensure DFT design rules and guidelines are met
  • Generate ATPG patterns
  • Verify ATPG patterns with gate-level simulation
  • Verify DFT scan test architecture and features
  • Conduct test coverage and test cost reduction analysis
  • Provide post-silicon support to ensure successful bring up and enhance yield learning
  • 8+ years of experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
  • Experience in debugging low coverage and DRC fixes
  • Proficient in logic design using Verilog
  • Experience in debugging test pattern issues
  • Support of Silicon bringup activities
  • Experience with post-silicon debug
  • Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc.
  • Experience with Tessent Scan/ATPG
  • Excellent presentation and inter-communication skills
  • Bachelor's or Master's degree in Computer Engineering/Electrical Engineering
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