Compiler Engineer - Algorithmic Workloads Compilation

Mythic-posted 3 months ago

11-50 employees

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Help push the boundaries of what can run on our accelerator. You’ll design compiler IRs and lowering strategies to support algorithmic workloads with irregular or dynamic control flow—loops, branches, and iterative methods—going beyond static neural networks. Working side by side with hardware engineers, you’ll influence ISA and execution model co-design to unlock new algorithm classes on analog and digital subsystems. The result: a compiler that makes complex algorithms practical to deploy while staying seamless for developers.

Extend compiler IRs to represent algorithms not easily captured in DNN graphs including control flow and iterative computation
Develop compilation strategies that unify analog compute with digital subsystems while maintaining performance and correctness
Prototype and optimize algorithms with irregular or dynamic control flow in compiler IRs, applying techniques such as vectorization, predication, and scheduling
Collaborate with hardware engineers to co-design ISA and features that improve support for algorithmic workloads
Define a roadmap for higher-level programming abstractions that simplify prototyping and accelerate deployment

3+ years of professional experience in compilers or high-performance systems software
Proficiency in modern C++ (C++14/17/20) and Python
Familiarity with compiler IRs (e.g., MLIR, LLVM, or equivalent) and their use representing complex program structures
Solid foundation in program analysis and optimization techniques (e.g., SSA form, loop optimizations, vectorization)

Hands-on experience developing MLIR or LLVM dialects for control flow (e.g. scf, cf) or affine/polyhedral representations.
Background in compiler-hardware co-design: working with hardware designers to refine ISA or execution models for efficiency
Proven ability to prototype irregular or control-flow algorithms in compiler IRs and optimize them for performance and resource constraints
Experience extending ML compiler stacks (ONNX, IREE, XLA, PyTorch, TVM) to support workloads beyond DNNs

The opportunity to make algorithmic and control-flow-heavy workloads practical on novel accelerator hardware.
A role that bridges compiler design and hardware co-design, shaping both the IR and the accelerator architecture.
A collaborative, innovative team that values engineering rigor, continuous integration, and user-focused design.
Competitive compensation, equity, and benefits package.

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Compiler Engineer - Algorithmic Workloads Compilation

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