Circuit Design Intern - Fall

Atomic Semi • San Francisco, CA

1d • Onsite

About The Position

Atomic Semi is building a small, fast semiconductor fab. It’s already possible to build this with today’s technology and a few simplifications. We’ll build the tools ourselves so we can quickly iterate and improve. We’re building a small team of exceptional, hands-on engineers to make this happen. Mechanical, electrical, hardware, computer, and process. We’ll own the stack from atoms to architecture. Our team is optimistic about the future and we want to continue pushing the limits of technology. Smaller is better. Faster is better. Building it ourselves is better. We believe our team and lab can build anything. We’ve set up 3D printers, a wide array of microscopes, e-beam writers, general fabrication equipment - and whatever is missing, we’ll just invent along the way. Atomic was founded by Sam Zeloof and Jim Keller . Sam is best known for making chips in his garage, and Jim has been a leader in the semiconductor industry for the past 40 years. About the role We’re hiring Circuit Design Interns for the fall term. The internship begins in September, with a preferred commitment of 4 to 8 months. We’re rebuilding the chip fabrication process from the ground up, so you’ll be exposed to some really interesting and impactful work. You’ll be directly responsible for the circuit design, standard cell layout, device characterization, and CAD flow development needed to support our internal design teams and future customers. You’ll work with NGSpice, K-Layout, OpenROAD + proprietary tools. Our philosophy is to get things built and tested in days or weeks, not months. Because of this, a portfolio is required to apply : show us the things you’ve actually built! If you’ve shipped a medium-to-high complexity system through a personal project or previous internship, you’d be a good fit here.

Requirements

• Pursuing a Bachelors Degree or higher in Electrical Engineering, Computer Engineering, or related fields
• Ability to learn quickly and troubleshoot technical problems
• Hands-on experience with analog and digital standard cell design, including layout, parasitic extraction, and design rule-driven physical verification
• Hands-on prototyping experience and the ability to move through design cycles quickly
• Familiarity with semiconductor processing: ALD, CVD, PVD, photolithography, etc.

Nice To Haves

• Knowledge of EDA tool flows, especially open-source flows like OpenROAD/OpenLane

Responsibilities

• Design and layout CMOS analog, mixed-signal, and RF circuit blocks
• Perform testing and characterization of CMOS test chips, including wafer probing
• Develop, validate, and refine CMOS device models to support circuit design and simulation accuracy
• Contribute to Process Design Kit (PDK) development and maintenance
• Conduct physical verification activities, including Design Rule Checking (DRC) and Layout Versus Schematic (LVS)

Benefits

• Housing Stipend to help with first month expenses
• Lunches daily, Dinners 3x per week, Stocked Office Kitchen with Snacks and Spindrifts
• Weekly Learning & Development opportunities
• Commuter Benefits including Parking and Late Night Uber rides from the office
• Paid Time Off inclusive of Holidays and Sick Time
• Visa Sponsorship
• Medical, Dental, and Vision insurance
• 401(k) retirement plan
• Life and Disability Insurance

What This Job Offers

• Career Level: Intern