Chiplet Physical Design Engineer

Nvidia•Westford, MA

51d

About The Position

NVIDIA has revolutionized computer graphics, PC gaming, and accelerated computing for over 25 years. It's a remarkable tradition of inventiveness driven by outstanding technology-and exceptional individuals. Right now, we are demonstrating the boundless capabilities of AI to build the forthcoming age of computing. A time where our GPU functions as the central intelligence of computers, robots, and autonomous vehicles capable of comprehending the environment. Doing what's never been done before takes vision, innovation, and the world's best talent. Joining the ranks of NVIDIANs means being part of a diverse and supportive setting that encourages everyone to strive for excellence. Join our team and discover how you can build a lasting influence on the world. NVIDIA is looking for a best-in-class Chiplet Physical Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a significant, growing and highly professional environment where you make a significant impact in a technology-focused company.

Requirements

Great teammate
BSEE / MSEE or equivalent experience.
8+ years experience in physical design
Experience in unit and top-level floor planning, bump and RDL layout, full-chip clock tree, power grid planning, and DRC/LVS.
In depth knowledge of physical design flows and methodologies (PNR, STA, physical verification).
Deep understanding of all aspects of Physical construction and Integration.
Knowledge in Physical Design Verification methodology LVS/DRC.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)

Responsibilities

Be part of a cross-business-unit team and own the high-speed IP integration.
Build a Chiplet floorplan layout design from early assembly/planning through implementation and signoff.
Work closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence.
Define and implement efficient, high-quality Chiplet level physical design tools, flows, and methodologies.
Gain hands-on experience implementing the partition-level BE design (RTL2GDS).