Cellular ASIC Design Engineer

Apple•San Diego, CA

About The Position

As a Cellular ASIC Design Engineer in Apple’s Hardware Technologies group, you will develop and optimize integrated-circuit design and implementation methodologies, focusing on area efficiency, power optimization, and design technology co-optimization. You will contribute to block-, IP-, and system-level products using advanced process technologies, including 3nm, 2nm, and beyond, and help improve Power, Performance, Area, and Cost efficiency. The role covers design-flow and methodology development, physical design and implementation, analysis and validation, power and performance optimization, cross-functional collaboration, and technical leadership. You will establish and maintain design standards, flows, scripts, and automation; improve timing convergence and design productivity; analyze design databases and silicon validation data; support advanced process technology bring-up; and drive methodology improvements across teams. The position also applies programming and, where relevant, machine-learning modeling to automate and improve design optimization and predictive analysis.

Requirements

Bachelor of Science degree or higher.
At least 10 years of relevant industry experience.
VLSI background with hands-on experience in RTL-to-GDSII flows.
Experience optimizing SoC Power, Performance, Area, and Cost.
Experience with SoC power flows and Vmin optimization.
Experience with Design Technology Co-optimization and identifying and solving scaling bottlenecks in new technology nodes.
Experience rapidly prototyping and scripting methodologies and implementing test-chip blocks.

Nice To Haves

Solid understanding of physical-design challenges.
Proficiency with synthesis and place-and-route tools and implementation exploration.
Experience with metal-stack optimizations.
Experience performing early technology-node analysis to identify implementation bottlenecks.
Expertise in Design Technology Co-optimization.
Strong analytical skills and ability to identify and communicate high-return-on-investment opportunities.
Ability to apply data science and machine-learning analytics to frontend and backend databases and post-silicon data to identify trends and patterns and refine implementation methodologies.

Responsibilities

Establish design guidelines, methodologies, and standards for synthesis, place-and-route, timing closure, and signoff.
Develop and optimize EDA tool flows for synthesis, physical implementation, and signoff.
Improve timing convergence processes across design teams to enhance design PPA and yield.
Create and maintain design flows, scripts, and automation tools to improve productivity and reduce turnaround time.
Identify physical-design utilization bottlenecks and develop architectural, design, and implementation solutions.
Collaborate with physical-design, CAD, IP, and Design Technology teams on timing closure and flow-script and tool development and validation.
Contribute hands-on to RTL-to-GDS digital flows and timing signoff for complex SoCs.
Conduct design technology co-optimization analysis, including operating-point analysis, scaling-trend analysis, and bottleneck identification in advanced technology nodes.
Run Spice simulations for PVT-corner validation and STA-to-Spice correlation.
Validate timing packages across advanced process technologies and develop timing signoff specifications.
Analyze design databases and silicon validation data to identify critical issues and improve design metrics.
Analyze digital, analog, and mixed-signal timing paths and constraints and provide solutions.
Develop voltage-scaling and power-optimization methodologies, including clock gating, power gating, and dynamic voltage/frequency scaling.
Use power-analysis tools for power signoff and optimization.
Drive STA methodology improvements using timing tools and ECO methodologies.
Collaborate with technology and IP teams on custom and semi-custom IP development.
Work with process technology, front-end design, physical implementation, CAD, and cross-functional teams to develop solutions.
Support advanced process technology bring-up from PDK through VLSI design production.
Improve DFT methodologies, including scan insertion, ATPG, and built-in self-test strategies.
Track industry trends and emerging technologies to improve design methodologies.
Use programming skills to automate and enhance methodologies.
Apply machine-learning modeling experience to design optimization and predictive analysis.