Cellular ASIC Design Engineer

Apple•San Diego, CA

46d

About The Position

As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power optimization, and design technology co-optimization. You'll design innovative products at the block/IP-level and system-level in advanced process technologies (3nm, 2nm and beyond). Your primary responsibilities will involve developing best-in-methodologies for optimizing Power, Performance, Area, and Cost efficiency metrics through various approaches: DESIGN FLOW & METHODOLOGY DEVELOPMENT: - Establish design guidelines, methodologies, and standards for synthesis, place-and-route, timing closure, and signoff processes - Develop and optimize EDA tool flows including synthesis tools (DC/DCT/DCG/Genus/Oasis), P&R tools (ICC2/Fusion/Innovus/Aprisa), and signoff tools (PT/PT-SI/Tempus) - Drive timing convergence process improvements across design teams to enhance design PPA and yield - Create and maintain comprehensive design flows, scripts, and automation tools to improve design productivity and reduce turnaround time PHYSICAL DESIGN & IMPLEMENTATION: - Identify utilization bottlenecks in physical design and develop architectural, design, and implementation-level solutions to improve utilizations - Work with physical design teams on timing closure, collaborating with CAD teams, IP teams and Design Technology teams for flow scripts/tools development and validation - Understand RTL to GDS digital flow and provide hands-on contribution for timing signoff of complex SOCs ANALYSIS & VALIDATION: - Perform design technology co-optimization analysis, including optimal operating point analysis for performance/power curves and identification of scaling trends and bottlenecks in advanced technology nodes - Conduct Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim) for PVT corners validation and STA vs spice correlation - Perform timing package validation across advanced process technologies and timing signoff specification development - Conduct in-depth analysis of design databases and silicon validation data to identify critical issues and improve overall design metrics - Understand intricate timing paths (digital, analog, mixed signal) and timing constraints, providing solutions as required POWER & PERFORMANCE OPTIMIZATION: - Develop and implement voltage scaling and power optimization methodologies including clock gating, power gating, and dynamic voltage/frequency scaling techniques - Use power analysis tools (RedHawk/SeaHawk/Voltus) for comprehensive power signoff and optimization - Facilitate and drive STA methodology improvements using industry-leading timing tools and ECO methodologies MULTI-FUNCTIONAL COLLABORATION: - Collaborate closely with technology and IP teams to enhance efficiency through custom and semi-custom IP development - Work closely with process technology, front-end design, physical implementation, CAD, and multi-functional teams to develop innovative solutions - Support advanced process technology bring-up from PDK to VLSI design production - Drive DFT (Design for Test) methodology improvements including scan insertion, ATPG, and built-in self-test strategies TECHNICAL LEADERSHIP: - Stay ahead of industry trends and emerging technologies to continuously improve design methodologies - Apply strong programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and enhancement - Apply ML modeling experience for advanced design optimization and predictive analysis

Requirements

Minimum BS and 10+ years of relevant industry experience
VLSI background with hands-on experience in RTL to GDSII flows
Prior experience in doing Power, Performance, Area and Cost optimizations for SoCs
Experience with SoC power flows & Vmin optimization
Experience with Design Technology Co-optimization, identifying and solving scaling bottlenecks in new technology nodes
Rapid prototyping and scripting of methodologies and test chip block implementation

Nice To Haves

Solid understanding of Physical Design challenges, proficiency with synthesis, place and route tools, and implementation exploration
Experience with Metal stack optimizations
Experience performing Early Tech node analysis to identify implementation bottlenecks
Design Technology Co-optimization expertise
Strong analytical skills and ability to identify and communicate high return on investment opportunities
Ability to apply data science and ML analytics for Frontend and Backend databases, as well as post-silicon data, to identify trends & patterns and fine-tune implementation methodologies

Responsibilities

Establish design guidelines, methodologies, and standards for synthesis, place-and-route, timing closure, and signoff processes
Develop and optimize EDA tool flows including synthesis tools (DC/DCT/DCG/Genus/Oasis), P&R tools (ICC2/Fusion/Innovus/Aprisa), and signoff tools (PT/PT-SI/Tempus)
Drive timing convergence process improvements across design teams to enhance design PPA and yield
Create and maintain comprehensive design flows, scripts, and automation tools to improve design productivity and reduce turnaround time
Identify utilization bottlenecks in physical design and develop architectural, design, and implementation-level solutions to improve utilizations
Work with physical design teams on timing closure, collaborating with CAD teams, IP teams and Design Technology teams for flow scripts/tools development and validation
Understand RTL to GDS digital flow and provide hands-on contribution for timing signoff of complex SOCs
Perform design technology co-optimization analysis, including optimal operating point analysis for performance/power curves and identification of scaling trends and bottlenecks in advanced technology nodes
Conduct Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim) for PVT corners validation and STA vs spice correlation
Perform timing package validation across advanced process technologies and timing signoff specification development
Conduct in-depth analysis of design databases and silicon validation data to identify critical issues and improve overall design metrics
Understand intricate timing paths (digital, analog, mixed signal) and timing constraints, providing solutions as required
Develop and implement voltage scaling and power optimization methodologies including clock gating, power gating, and dynamic voltage/frequency scaling techniques
Use power analysis tools (RedHawk/SeaHawk/Voltus) for comprehensive power signoff and optimization
Facilitate and drive STA methodology improvements using industry-leading timing tools and ECO methodologies
Collaborate closely with technology and IP teams to enhance efficiency through custom and semi-custom IP development
Work closely with process technology, front-end design, physical implementation, CAD, and multi-functional teams to develop innovative solutions
Support advanced process technology bring-up from PDK to VLSI design production
Drive DFT (Design for Test) methodology improvements including scan insertion, ATPG, and built-in self-test strategies
Stay ahead of industry trends and emerging technologies to continuously improve design methodologies
Apply strong programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and enhancement
Apply ML modeling experience for advanced design optimization and predictive analysis