Camera DV Engineer

Qualcomm-posted 3 months ago
$148,300 - $222,500/Yr
Mid Level
San Diego, CA
Computer and Electronic Product Manufacturing
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At Qualcomm, we invent breakthrough technologies that transform how the world connects, computes, and communicates. You interact with products and technologies made possible by Qualcomm every day. Qualcomm is a Technology Platform company known worldwide for its Snapdragon platform providing solutions in Wireless connectivity and Multimedia along with Compute, IoT, Automotive and AI - and this is where you come in as a Design Verification Engineer in the Snapdragon Sight team. Camera Image processing has evolved to become an integral part of our daily life creating everlasting connected memories and assisting innovative devices through human and computer vision technologies. Our team delivers the Camera ISP to majority of Android Eco-system Smartphones, AR/VR and IoT devices, provides Imaging & vision solutions for automotive platforms across ADAS & infotainment applications to world-wide Automotive manufacturers. It's an opportunity to be part of the team that creates highly advanced/specialized Camera ISPs and consistently ranks as the best Imaging solution. Join us for a limitless opportunity to learn, grow and lead the world of Imaging and design verification.

  • Engage in Technical discussions across the multiple cross-functional teams.
  • Participate in Algorithm development and review / influence optimal imaging solutions.
  • Engage & review specifications and data flows with Design & Architects.
  • Collaborate towards end-to-end product development with Software & Firmware team.
  • Implement new or increment test benches to adapt to new requirements by extensively applying object-oriented concepts & UVM methodology.
  • Write parameterized & scalable verification plans.
  • Write complex constraints and sequences to create corner case Algorithm and pipeline tuning scenarios.
  • Verify functionality as well as Use-Case Power & Performance KPI's are met.
  • Use Simulation/Formal/Assertion/Emulation flows to close on Functional and Code coverages.
  • Debug complex issues across multiple verification platforms.
  • Bachelor's degree in Engineering, Science, or a closely related field with 3 - 9 years of experience.
  • Experience with design verification defining test plans, developing verification infrastructure using OOP and execution of defined test plans to meet required Metrics of Closure.
  • Expertise with Hardware verification languages (HVL) such as System Verilog testbench (OVM/UVM).
  • Development of Directed and Constrained Random stimulus.
  • Strong Digital Design concepts and debugging skills with expertise in traversing Verilog/System-Verilog RTL.
  • Master's degree in engineering, Science, or a closely related field with 1 - 7 years of experience.
  • Good understanding of Object-Oriented Programming (OOP) concepts.
  • Exposure to Formal flows.
  • Programming proficiency - HDL, HVL, system Verilog/UVM, C/C++.
  • Scripting proficiency - Perl, Python, TCL, Shell.
  • Experience with Verification of Complex IP/Subsystem/SOC with exposure to End-to-end verification methodologies.
  • Excellent written and verbal communication skills to work in a collaborative environment with geographically distributed teams.
  • Experience with simulation acceleration and emulation platforms is a plus.
  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Comprehensive benefits package designed to support success at work, at home, and at play.
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