Camera Design Engineer

Qualcomm • Santa Clara, CA

6d

About The Position

The Multimedia Camera HW team is looking for strong ASIC design engineer for an exciting opportunity to be involved in the design of world class image and video processing blocks. As a member of team, the candidate will be responsible for the following: Collaborate with hardware/system architects to micro-architect/design HW specific to Multimedia and Camera Image Signal Processing algorithms Own and deliver core level IP and Camera Subsystem RTL design Run synthesis, review results to ensure desired QoR is met. Perform design rule checks, low power checks, cross-clock-domain (CDC) checks. Evaluate performance, area, power, and system cost tradeoffs Work closely with design verification engineers to develop test plans and reference bus-functional models Implement and debug tests at both the module and core level throughout the development cycle Create and maintain design documents. The environment is fast-paced and requires cross-functional interaction on a daily basis. So good communication, planning and execution skills are a must.

Requirements

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 6+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 5+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
• Ideal candidate to have 5+ years of industry exp. in: Verilog or VHDL RTL design
• Design Verification
• Bus protocols like AHB, AXI
• Image, Video, Graphics, Multimedia Processing, or DSP
• Experience with RTL sanity tools specific to Design Rule Checking, Clock Domain Crossing checks, Synthesis, Timing analysis, Low power checks(CLP)

Nice To Haves

• Experience with System Verilog or System C
• ASIC implementation of Image Processing Camera IP
• Experience working with synthesis and physical design teams
• TCL/Perl/Python/shell-scripting skills a major plus

Responsibilities

• Collaborate with hardware/system architects to micro-architect/design HW specific to Multimedia and Camera Image Signal Processing algorithms
• Own and deliver core level IP and Camera Subsystem RTL design
• Run synthesis, review results to ensure desired QoR is met.
• Perform design rule checks, low power checks, cross-clock-domain (CDC) checks.
• Evaluate performance, area, power, and system cost tradeoffs
• Work closely with design verification engineers to develop test plans and reference bus-functional models
• Implement and debug tests at both the module and core level throughout the development cycle
• Create and maintain design documents.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees