CAD Engineering, Principal

MACOM Technology Solutions Holdings, Inc.Milpitas, CA
1d

About The Position

In this role layout engineer with closely work with analog design team to layout and verify custom analog/mixed-signal IPs Lead full-custom IC layout design and verification, including chip floor planning, analog IP layout and chip level layout integration of various analog, mixed signal and ASIC blocks Full verification of Block level and top-level layout including extraction, DRC, LVS, and DFM checking Layout schedule planning and working with other IP layout engineers to integrate various layout blocks Co-work with designers on block level and top-level floor planning Layout review for power/gnd routing, electro migration, signal path check, matching, and signal coupling

Requirements

  • B.S./M.S. in Electrical Engineering or related coursework.
  • Minimum 7 years' experience in Semiconductor based companies with custom layout experience.
  • High-speed Mixed-Signal layout design expertise
  • Knowledge of Cadence Virtuoso design flow
  • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS reports.
  • Full understanding of IR drop, RC delay, Electro migration and chip finishing
  • Ability to support a product through the entire product development and release cycle
  • Ability to do floor planning and do area estimate
  • Excellent collaborative skills with circuit designer and other layout engineers
  • Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels
  • Willingness to travel when required.

Nice To Haves

  • Familiarity with high-speed BiCMOS layout is a plus
  • Scripting in Cadence is a plus

Responsibilities

  • layout and verify custom analog/mixed-signal IPs
  • Lead full-custom IC layout design and verification, including chip floor planning, analog IP layout and chip level layout integration of various analog, mixed signal and ASIC blocks
  • Full verification of Block level and top-level layout including extraction, DRC, LVS, and DFM checking
  • Layout schedule planning and working with other IP layout engineers to integrate various layout blocks
  • Co-work with designers on block level and top-level floor planning
  • Layout review for power/gnd routing, electro migration, signal path check, matching, and signal coupling

Benefits

  • Health, dental, and vision insurance.
  • Employer-sponsored 401(k) plan.
  • Paid time off.
  • Professional development opportunities.
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