Cache Coherence Management Unit Micro-architect and Design Engineer

ARM-posted about 2 months ago
Full-time • Mid Level
Austin, TX
5,001-10,000 employees
Professional, Scientific, and Technical Services
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Are you ready for a new and exciting challenge? If you are a self-motivated and experienced micro-architecture and logic design candidate looking to make a difference in an innovative and inclusive team, you've come to the right place! The candidate will join the System IP Coherent Interconnect design team responsible for the development of several innovative and powerful AMBA based IPs for the Infrastructure, IoT, and Automotive line of business. The candidate must have hands-on design experience with Cache Coherency Management Unit (Full Coherent Home Node) for high performance interconnect. Candidate must be highly skilled in cache, coherency, snoop filter design. The candidate must have a detailed understanding across all design aspects to deliver successful IP with optimal PPA. This includes low-power design techniques and an awareness of the impact of design decisions on system performance.

  • Involvement in micro-architecture and logic implementation for Cache Coherency Manager Unit using System Verilog RTL coding
  • Planning, tracking, and coordinating of individual tasks to meet high quality goals at the planned milestone
  • Working closely with design and verification teams to share the responsibility of delivering high quality hardware designs, including debugging functional or performance issues using simulation and debug tools
  • Collaborating with other involved teams including software and 3rd party
  • Improving design methodology across the System IP group and wider Arm design community
  • Providing direction and mentoring to other junior members of the team
  • Highly skilled in Micro-architecture and design experience in cache coherence management unit, Snoop filter, cache, fabric for high performance and high-speed interconnect design
  • Deep working knowledge of topics including transaction ordering, virtualization, and coherence
  • Knowledge of high-speed interfaces such as AMBA CHI and/or AXI
  • Familiarity with parameterized design techniques for scalable IP
  • History of high quality, low power, powerful complex micro-architecture and RTL implementations in reasonable timescales
  • Experience with synthesis, static timing, and DFT
  • Experience with physical design and verification methods
  • Strong communication, collaboration, and presentation skills
  • Minimum Bachelors or Masters degree in Computer Engineering/Electrical Engineering
  • Familiarity with PCI Express (PCIe), Ethernet, DDR is a plus
  • Experience with scripting languages like Perl, Ruby, etc, and competence with Unix/Linux, shells, and Makefiles is a plus
  • ARM is architecting a dynamic place where people love to work.
  • Be part of ARM Austin-based Interconnect team and engage with the world's most famous technology companies
  • This team's mission is crafting scalable IP for connected AMBA-compliant SoC connectivity and can be customized for multiple performance points.
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